(1) Field of the Invention
The present invention relates to a method for making high-density integrated circuits for ultra large scale integration (ULSI) on semiconductor substrates, and more particularly relates to a method for forming reliable stacked and borderless via structures for multilevel metal interconnections.
(2) Description of the Prior Art
The high density of integrated circuits formed on semiconductor substrates for ULSI requires multilevels of metal interconnections for electrically interconnecting the discrete semiconductor devices on the semiconductor chips. A dielectric layer, usually referred to as the Poly/Metal 1 Dielectric (PMD), is deposited over the field effect transistor (FET) polysilicon gate electrodes and substrate contacts to electrically insulate the devices from the next patterned metal layer. The different levels of metal interconnections are then formed and separated by layers of insulating material, commonly referred to as Interlevel Metal Dielectric (IMD) layers. Both the PMD and IMD layers are commonly referred to as the InterLevel Dielectric (ILD) layers. These interposed dielectric (or insulating) layers have etched contact holes in the PMD layer to the underlying semiconductor devices and vias holes in the IMD layers which are used to electrically connect one level of metal to the next level of metal. The via holes are also commonly referred to as simply vias.
As the circuit is scaled down in ULSI technology to smaller dimensions, one of the most difficult obstacles to continued downscaling is controlling the level-to-level alignment of the photolithography. This is especially a problem in the complex structure of the interconnecting metal and vias as minimum device feature sizes reach 0.18 micrometers. Consequently, the packing density of the metal lines becomes limited by design ground rules governing the separation of the contact holes and/or vias from another level. Specifically, the design rules limit the nesting (stacking) of contact holes or vias in the ILD layer between the various levels of patterned conducting layers.
To better appreciate the advantages of using stacked and borderless contact holes and via structures, a sequence of schematic top views for the design layout of two levels of patterned metal and interconnecting vias is shown by the prior art in FIGS. 1A-1D for different design ground rules. In all figures an insulating InterLevel Dielectric (ILD) layer 14 is deposited, and contact holes or vias 4 are etched in the ILD layer 14 to the substrate 10, or to a patterned conducting layer (not shown) on the substrate. A patterned first metal layer 20 is formed on the ILD layer 14 over the vias 4, and a second ILD layer 14' is deposited to insulate the patterned metal layer 20. Vias 4' are etched in ILD layer 14' to the metal layer 20 and a second metal layer 20' is patterned to form the second level of metal interconnections. The metal lines in FIG. 1A have borders (wider metal lines 20 and 20') to accommodate misalignment of the vias 4 and 4', and also the vias are not stacked (one over the other), and therefore require the larger design layout area. The metal lines in FIG. 1B do not require design rule separation between metal lines on different levels for via holes 4 and 4', and require less area. FIG. 1C shows stacked vias with metal borders, FIG. 1D shows borderless vias without via stacking, and FIG. 1E shows stacked and borderless via structures. It is clearly seen from FIG. 1E that the stacked and borderless via structures provide a space-saving advantage, which is a reduction of about 62% in area compared to the structure in FIG. 1A. Therefore, it is very desirable to form stacked and borderless via structures that reduce the total area occupied by the metal interconnections by about 62%. This allows for a substantial increase in the packing density of devices on the semiconductor substrate.
Unfortunately, several processing problems arise when stacked and borderless via structures are fabricated. These process problems are best illustrated by referring to the prior-art schematic cross-sectional views in FIGS. 2A-2D, FIGS. 3A-3C, and FIGS. 4 and 5 showing two-levels of metal having vias.
FIGS. 2A-2D depict the problems with making stacked vias. In FIG. 2A no metal plug is used in the vias 5' and can result in poor electrical contacts at point 5 causing current-crowding and electromigration of metal atoms, while a good metal plug 3, as in FIG. 2B, ensures good via contacts at 3'. A poorly formed metal plug 3, as in FIG. 2C, can also result in poor via contacts, making contact only at point 6. FIG. 2D shows a three-level metal structure with good metal plugs 3 and good via contacts, but unfortunately requires design rules for metal borders to prevent misalignment, that would otherwise occur, as shown in FIG. 3 when borderless vias are used.
The problem of forming borderless via structures using a conventional dual-Damascene process is best illustrated with reference to FIGS. 4A and 4B.
In the conventional dual-Damascene process, as shown in FIGS. 4A and 4B, a trench 4 is partially etched in the ILD layer 16, and a second photoresist mask (not shown) is used to etch the via 2 in layer 16 to the underlying metal 20. The trench 4 and via 2 are filled with metal 20' and etched or polished back by chemical/mechanical polishing (CMP) to the surface of layer 16. However, as shown in the top view of FIG. 4A, when the etched via 2 is misaligned to the trench 4, as occurs in borderless vias, then as shown in the cross sectional view in FIG. 4B, contact area B is very small resulting in high contact resistance. The problem in FIG. 4B is depicted for the cross section through 4B-4B' of FIG. 4. For example, in the 0.18 um technology, the metal line widths are about 0.2 um, and a misalignment of 0.1 um would result in a contact that is only 0.1 um wide.
Various methods of making stacked borderless contacts have been reported in the literature. For example, C. Y. Chang, S. M. Sze in ULSI Technology, McGraw-Hill Co., Inc., 1997, pp. 446-447 discuss the methods and associated problems with making stacked and borderless via structures. See the prior-art structures in FIGS. 1A-1E and 2A-2D. Yew et al. in U.S. Pat. No. 5,801,094 describe a dual-Damascene process using a single etch-stop layer for making trenches and borderless contacts. Another method is described by Bronner et al., U.S. Pat. No. 5,792,703, for making borderless self-aligned electrical contacts to diffused device regions in a substrate, and for making bordered contacts to the self-aligned contacts. Barber et al., U.S. Pat. No. 4,966,870, teach a method for making borderless contacts but do not address the dual-Damascene process. Cronin et al. in U.S. Pat. No. 5,466,636 teach a method for making borderless contacts using a removable mandrel, but do not address the dual-Damascene process.
There is still a strong need in the semiconductor industry for providing a simplified method for forming self-aligned stacked and borderless via structures between the patterned metal levels which are not limited by the design rules.